**Homework Assignment #4**

**EE477 Spring 2014** Professor Parker

Hardcopies due in the course boxes on the third floor of
EEB 5 PM 3/12/14

Ecopies due 5 PM 3/12/14 using the "Assignment" Function
on DEN

**To ensure academic privacy, please use a cover page on your
homework hard copies that does not contain any work.
Turn in EITHER a hard copy or ecopy, not both.**

Assume for the problems below
that

V_{dd}= 1.8 V, V_{tp} = - 0.4 V, V_{tn} = 0.4 V, V_{tp,BE}
= - 0.5 V, and V_{tn,BE}
= 0.5 V.

T_{ox}_{ }=
41 angstroms for thinox, and 5000
angstroms for thick oxide.

ε_{0} (epsilon) = 8.85 X 10 ^{-14} F/cm
and ε_{oxide}(epsilon) = 3.9.

lambda = 0.1 micron.

C_{jbsn} = 9.725 x
10^{-4} pF/ μm^{2} and C_{jbswn}
= 2.27 x 10^{-4} pF/ μm
(micrometer). Assume drain is the same.

C_{jbsp} = 11.57 x
10^{-4 }pF/ μm^{2} and C_{jbswp}
= 1.8 x 10^{-4} pF/ μm
(micrometer). Assume drain is the same.

x_{j} (diffusion
depth) = 0.1 microns.

Assume ß_{n} (k_{n})=
219.4 W/L µ A(microamps)/V^{2} and ß_{p} (k_{p})=
51 W/L µ A/V^{2}

1. (10%) a) Describe
how the input/output voltage characteristic transfer curve of
the inverter appears when the PMOS and NMOS transistors are
equal in size.

b) If you could improve noise margin, what would be the best
way to size the PMOS transistor, assuming the NMOS transistor
is unit size?

^{ 2. (10%) Size a
3-input NOR gate }^{for equal rise/fall
times in the worst case.
}

^{ 3. (10%) }^{What
is the ratio between the RC time constant of the rise to fall
time in the worst case if you build a 5-input NAND with
only unit size transistors? Note: all transistors are
unit size, including PMOS transistors. }

^{Note: Lecture 15, to be presented 3/6/14, will cover techniques needed to solve problems 4-8, below.
}

^{ 4. (15%) Use the compound
gate shown below. Label all drains and sources. Show an
identical Euler path for both NMOS and PMOS transistors by
listing transistor inputs on both paths. If you cannot find
a complete Euler path, you might need to add an extra
transistor or two. Do not rearrange the transistors.
5. (20%) Give a stick diagram for the compound gate in
Problem 1 above, using the Euler path you found.}

^{6. (10%) Size the devices
in the longest paths in the compound gate to give equal rise
and fall times in the worst case. Note: in case
you added extra transistors, then you need to size
the compound gate with the extra transistors.
}

^{7. (10%) }How
many diffusion capacitances get charged/discharged in the worst
case that affects the output node, assuming no diffusion regions
are shared?^{ }

^{8. (15%) A design has
a number of common inputs/outputs that need to be connected.
Use the left edge algorithm to connect common inputs using
as few tracks as possible. The starting and ending positions
of each common input are given below. You can assume the
inputs come from either the top or the bottom of the channel
to make the problem easier. If two wires start or end
at the same point that does NOT mean they are or should be
connected.
A (1,4)
B (3,6)}

^{C (4,9)
D
(5,10)}

^{E (9,12)
F
(7,14)}

G (11,12)^{}

H (10,12)^{
I (11,13)
}