Electrical Engineering 577b
VLSI Design Projects Class

Fall 2001
OHE 100, Studio D, Tu/Th 5:00-6:20pm
WWW: http://www-classes.usc.edu/engr/ee-s/577bb/ee577b.html

Bulletin    Staff Info    Overview    Syllabus    Project   Grading    Homeworks    Tools    Discussion Forum    Texts    Exams    Policies


  • HW#1 has been assigned (9/5/2001). Due is 9/13/2001.
  • EE577B Discussion Forum has been added. Ask your question here.
  • HW#2 has been assigned (9/18/2001). Due is 9/27/2001.
  • HW#1 Grade is available. (9/19/2001)
  • New Discussion Forum is available. (9/19/2001)
  • HW#3 has been assigned (9/27/2001). Due is 10/11/2001.
  • HW#3tips are available.(10/04/01).
  • HW#4 has been assigned (10/16/01). Due is 10/25/01.
  • HW#4 presentation is available.(10/16/01).
  • HW#2 Grade and HW#2 grade sheet are available. (11/04/2001)
  • Final Grade is available. (12/20/2001)
  • Upcoming talk on asynchronous circuits: "Event Dynamics" by Mark Greenstreet (UBC): EEB 248, Friday, Oct. 26th, NEW TIME 10:00am.
  • HW#4 DEMO re-schedule: Thursday (DEC/06) at SAL in the afternoon (3:00 to 4:00pm). Look for Marcos. Bring your HW#4 report.
  • FINAL REPORT AND PRESENTATIONS: Final Report is due Dec/13/01 (no delay allowed) All presentations must be done on Dec/11 (Studio B) from 4:30 to 6:30pm or Dec/13 (room EEB 349) from 6 to 8pm.

  • Instructor

    Teaching Assistants


    This course has two main thrusts. The first is to teach several advanced topics in VLSI circuit design with particularly emphasis on asynchronous circuits. This new technology has been in its research stages for the last 15 years and is now being actively used commercially, including a company in which I am heavily involved. This is the first year that I will be actively teaching asynchronous design in VLSI and I hope that you will find it as fun as I do.

    Topics will include

  • Behavioral modeling of asynchronous systems using Verilog
  • Fine grain pipelining and pipeline (slack) optimization
  • Structural design of asynchronous modules
  • Timing analysis using Petri nets and Signal Transition Graphs
  • Quasi-delay insensitive and timed circuit design In addition to asynchronous design, I plan to review and go into greater depths in
  • Deep submicron challenges: resistance, capacitance, inductance
  • Advanced domino and dynamic logic design
  • Low power techniques, including low-swing signaling
  • Advanced memory design
  • High-speed synchronous clock distribution and clocking methodologies The second thrust is to use some of these techniques in a significant full-custom team project. This year the plan is to design an ASIC for a programmable finite impulse response (FIR) filter, a standard task in many digital signal processing systems. This will involve behavioral and structural Verilog, transistor-level design and schematic entry using Cadence, HSPICE simulations, manual floor-planning and wire diagrams, and magic layout, extraction, and simulation.


    EE577a required. EE552 and EE557 recommended. Proficiency in a high-level programming language required.  


    Click here to see this years syllabus. 


    None initially planned, but depending on student progress there may be a midterm.  

    Computer Tools

    We will be using a variety of tools including, Cadence, Magic, Verilog, and HSPICE. See here for more documentation of the tools we will use in the class. 

    Recommended Reference Text Books

    Digital Integrated Circuits, A Design Perspective, by Jan M. Rabaey

    Principles of CMOS VLSI Design , Weste & Eshrighan

    Selected readings on and off the web (see the syllabus for individual links).


    Project 40%
    Homework&Midterm 60%


  • HW Grade
  • HW#1  Due 9/13/2001
  • HW#2  Due 9/27/2001
  • HW#3  Due 10/11/2001
  • HW#4  Due 10/16/2001

  • Academic integrity

    The USC Student Conduct Code prohibits plagiarism. All USC students are responsible for reading and following the Student Conduct Code detailed in SCampus.

    The projects must be done in teams of up to three. Teams cannot share material with other teams. Homeworks must be done independently. If, however, you or your team is stuck on a particular concept, use of CAD tool, or specific problem with the projects, please ask a fellow student, the TA's or me. You can get the key concepts you need and then work independently. I don't want you to waste you time in confusion. If the collaboration is significant you should cite the collaboration, i.e., "Joe Smith helped me understand this." I consider copying projects or excessive collaboration cheating and this will not be tolerated. You should produce your projects independently. Do not copy computer files. Similarly, if you get an answer from a textbook other than the required text, you should cite it. Otherwise, this is considered plagerism. First penalty on cheating of any kind will be to receive a "0" on that homework. This applies to both the student who copied/plagerized and the student who let his paper be copied.

    Some examples of what is not allowed by the conduct code: copying all or part of someone else's work, and submitting it as your own; giving another student in the class a copy of your assignment solution; consulting with another student during an exam. If you have questions about what is allowed, please discuss it with the instructor.

    Violations of the Student Conduct Code will be filed with the Office of Student Conduct, and appropriate sanctions will be given.

    World Wide Web:

    This document in front of you (which is also the class home page) and other course materials are available on the Web. This page will eventually be accessible from the EE Department Course Information page, and from the instructor's home page. Links to other course materials will be added as the semester progresses. 
    Various parts of this web page created by cutting and pasting parts of web pages created by Clare Bono and Doug Ierardi. Last modified Aug. 2001 by Peter Beerel, pabeerel@usc.edu. Contents subject to change with no notice.